Cyclone V SoC - Shared Memory Controller

Thanks for the reply thepancake, I have just discovered that the reason waitrequest was high. The preloader file needs to be updated following the change to the HPS component to add the FPGA to HPS SDRAM port to the HPS SDRAM controller configuration. My problem was that the preloader did not correctly re-generate (see below).

Apparently you need to delete the entire spl-bsp directory before generating the pre-loader. When I attempted to make the preloader generating in bsp-editor, then running the makefile in the spl-bsp directory, the generated preloader file (preloader-mkpimage.bin) did not change. Once I deleted the entire spl-bsp folder and re-generated, this time the preloader file was changed. Once I ran using this pre-loader, the SDRAM to FPGA avalon interface appears to work normally (i.e. waitrequest is low until the controller is busy).

However, the problem I am now having is that when I attempt a read from the FPGA I cause the system to crash (terminal freezes and HPS requires a hard reset) and no data is returned to the FPGA (Read Valid is never set) Possibly I am attempting to access an area of RAM that I shouldn't be?

I am not certain of how the HPS SDRAM maps to the avalon interface but the area I am trying to access is the area that I think is being assigned by the rocketboards example module http://www.rocketboards.org/foswiki/.../myfirstmodule