Cyclone V SerialLite-II

Hello all,

I am trying to impement SerialLite-II on a Cyclone V. I have my design to the point where I can simulate it successfully, but synthesis fails with the following error:

warning: outclk port on the pll is not properly connected on instance main_pll:u_main_pll|main_pll_0002:main_pll_inst|altera_pll:altera_pll_i|general[0].gpll. the output clock port on the pll must be connected.

info: must be connected

error: hssi pma tx buffer node 'impl_top:dut|sl2_top:u_sl2_top|xcvr_phy:u_xcvr_phy|altera_xcvr_custom:xcvr_phy_inst|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'dataout' port. it must be connected to one of the valid ports listed below.

info: can be connected to i port of arriav_io_obuf wysiwyg

error: hssi pma rx buffer node 'impl_top:dut|sl2_top:u_sl2_top|xcvr_phy:u_xcvr_phy|altera_xcvr_custom:xcvr_phy_inst|av_xcvr_custom_nr:a5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf' is not properly connected on the 'datain' port. it must be connected to one of the valid ports listed below.

info: can be connected to o port of arriav_io_ibuf wysiwyg

info: can be disconnected

Altera changed the way the core is created with the V-series and separated the PHY from the core in the megawizard. This may add more flexibility in the design, but certainly adds more complexity (and room for error) in the connections between the blocks. I particularly enjoyed the reference in the error to ArriaV...

Has anyone out there been successful with their SerialLite implementation on Cyclone V? Any insights?

Thanks in advance!