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From the Transceiver Clocking document (
http://www.altera.com/literature/hb/cyclone-v/cv_53002.pdf):
"When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central
clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you
can use the channel only as a transmitter channel."
One of the central transceivers has to be used for the local clock divider for full-duplex use. You get to pick which, but the one that you pick can only be TX afterwards (so no full-duplex).
The design is not mine, but a reference design provided by Altera SR. The reconfiguration controller (I assume that is what you are asking about) is required even if you don't want to use reconfiguration. As long as the reference clock is the same for all channels/protocols, one reconfiguration controller may be shared across all transceiver channels. Just change the reconfiguration controller IP in the MegaWizard to match the reconfiguration inputs to your module. Remember that you need one reconfiguration interface per discrete link, and one per channel in the link. For example, with a x4 PCIe link, I need 5 reconfiguration interfaces (1 for link, 4 for each lane). With four x1 SerialLite-II links, I needed eight reconfiguration interfaces. And so on...
Hope this helps.
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Can I get your email address for a few more questions if you don't mind? Thanks!
Honored Contributor
