Forum Discussion

Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone V PLL issues

I'm trying to obtain a 148.5MHz clock from a PLL using a 50MHz source. Currently the PLL has no output and the lock signal is low. I'm using Quartus 18.1 as version 20 seems to be very broken when ...
  • Mikexx's avatar
    Mikexx
    5 years ago

    The PLL is now working.

    This PCB has been a little disaster. VCCBat was left unconnected so we couldn't program the device. This was drilled through from the bottom (the joys of BGAs) to the copper pad under the solder ball and a connection made. Unfortunately made to the FPGA 3.3V supply. Why 3.3V? Because it was convenient and was within the max working voltage on VCCBat.

    We also discovered that the Vref pins are left disconnected. These should be connected to GND or the respective bank power supply and it's not clear what leaving them floating will have?

    The 3.1V on the RREF_TL was perhaps an indicatio there was a problem and perhaps connected in some way to VCCBat.

    After some careful moving of the power to VCCBat from 3.3V to 2.5V I noted the voltage on RREF_TL pin was now at 0.7V, and after loading a basic test SOF file the PLL now works.

    Many thanks for your post. T5 is connected as per the rest of the VCC_FPLL pins. I was noting an anomaly on a data sheet that caused me some concern.

JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi @Mikexx

Im not sure about the VCC_FPLL there? Do you mean you already have it connected correctly to T5 (in fact there is a bunch of them

M3
T3
T5
F4
U18
H19

Is it all the pll are not working?

Is it intermittent locking/not-locking?

Is it only 148.5Mhz is not locking? Changing to other output frequency works?

  • Mikexx's avatar
    Mikexx
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    The PLL is now working.

    This PCB has been a little disaster. VCCBat was left unconnected so we couldn't program the device. This was drilled through from the bottom (the joys of BGAs) to the copper pad under the solder ball and a connection made. Unfortunately made to the FPGA 3.3V supply. Why 3.3V? Because it was convenient and was within the max working voltage on VCCBat.

    We also discovered that the Vref pins are left disconnected. These should be connected to GND or the respective bank power supply and it's not clear what leaving them floating will have?

    The 3.1V on the RREF_TL was perhaps an indicatio there was a problem and perhaps connected in some way to VCCBat.

    After some careful moving of the power to VCCBat from 3.3V to 2.5V I noted the voltage on RREF_TL pin was now at 0.7V, and after loading a basic test SOF file the PLL now works.

    Many thanks for your post. T5 is connected as per the rest of the VCC_FPLL pins. I was noting an anomaly on a data sheet that caused me some concern.

    • JonWay_altera's avatar
      JonWay_altera
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi @Mikexx Thanks for updating me the rootcause of the problem.

      Btw, for your concern, it seems that different package use different pins (T4 vs T5) for VCC_FPLL, what is the anomaly? What is the expectation?

      • Mikexx's avatar
        Mikexx
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Ok, I'm using the 5CEBA2F23C8 where the F signified the FineLine BGA This uses T5. The U package, with the same number of pins, is similar but uses T4.

        I was taught it was good engineering practice to make the same where possible, but where there was a deviation to make it a subtle and noticeable one.