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Re: Output Voltage Higher than Maximum Voltage of GPIO
@Luckyguide wrote: I can try to lower the amps, I don't believe the current is particularly relevant. @Luckyguide wrote: but I can’t change the slew rate. Yes, there is only 1 destination pin. Ok @Luckyguide wrote: I hope my question can be answered as to how the output voltage can even reach 4.7V if I only send a 1 or a 0 from my program. Theoretically it should then only be 0-3.3V maximum with perhaps a little overshoot? I have already answered this. If an unterminated transmission line is driven, then the reflected voltage will return and add to the source drive voltage. I recommend you look up about this. An example article: https://wiki-power.com/en/%E4%BF%A1%E5%8F%B7%E5%AE%8C%E6%95%B4%E6%80%A7-%E5%A4%B1%E7%9C%9F/#reflection-at-resistive-loads2.4KViews0likes1CommentRe: Output Voltage Higher than Maximum Voltage of GPIO
@Luckyguide wrote: Thanks for your response, The signals are not terminated, and I don't have a good reference signal to compare to. I tried making a reference with a lower frequency of 3KHz but that also showed the same problem with voltage overshoot. The current is what i specified in the pin planner, I didn't measure it during the test. I'm not quite sure about the protection diodes, as I couldn't find any information about it anywhere. The trace is 10cm if you're referring to the cable length of the GPIO to the oscilloscope probe. The MAX 10 does not have an internal source resistance capability and I would prefer to not make any circuit changes, as I am wondering why the direct output at the GPIO is not a 50% duty cycle 3.3V PWM signal. Isn't it that this constant overshooting will damage the GPIO of the development board over time if I don't fix the overshoot at the GPIO? I am aware that I can add capacitors and resistors to stop the overshoot, but I am rather concerned about the behaviour of the development board and I feel like either I have done something wrong in pin planning or I am missing something. So the overall device current. That trace is very long. Simple transmission line theory suggests with an o/c destination the trace will go to 2 x VCC or in your case the voltage is probably limited by protection diodes ~5V. Therefore I might expect to see a nominal 2.5V average. Can you change the drive current, or the slew rate? I would set these to be the lowest and slowest. I know you don't want to change the PCB, but you should think transmission line and termination for all signals, especially when driven with sub-ns rise and fall times. 10cm represents a time of ~0.5ns. I hope there is just one destination pin? A series termination at the source would be best, the alternative is a parallel termination at the destination. The overriding consideration is does the system work as intended?2.5KViews0likes3CommentsRe: Output Voltage Higher than Maximum Voltage of GPIO
I presume the signals are not terminated? I would also keep an open mind over the integrity of measurement in terms of probe and 'scope. Do you have a reference signal on the board to compare with? Do you really mean either 8 or 4 Amps? How are you measuring this current? Can you elaborate on the context of this current? Is the Max10 device output limited by protection diodes that don't clam to your 3.3V VCC? In which case 4.7V is quite realistic on account of a reflection. How long is the trace? Does the Max10 have an internal source resistance capability? Can you load the PWM output at the signal destination?2.5KViews0likes0CommentsRe: Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock
I can confirm I have used signal tap to verify the cntsel[4:0] bits within the PLL module, the horses mouth so to speak, and they are set as expected. The cntsel[4:0] are not static, but it seems that synthesis will move the bits to suit. Driving gignals are confirmed as per "Figure 5: Waveform Example for Dynamic Phase Shift with Altera PLL IP Core" in "Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores". A waveform is attached to an earlier post. What is especially curious is that more than one cntsel[4:0] value will affect the same clock. There is a throw away mention in the above document: "When the PLL has two clocks with 0 degree initial phase shift between the clocks, the Fitter synthesizes away the second clock automatically. To prevent the clocks from merging, Altera recommends manually performing location constraint for each of the PLL output counters which share the same frequency and phase shift". How would I do this? Are there any examples?2.6KViews0likes1CommentRe: Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock
Many thanks for the reply. I'm using Version 20.1 While I could check the RTL more than one selection of cntsel[] seems to affect the same clock. Furthermore there are some output clocks that do not change independent of whichever cntsel[] is active.2.8KViews0likes0CommentsRe: MAX 10 JTAG programming
I know I am not directly answering your question, but .......... I was wondering if you were reliant on the JTAG pullups for a logic high, or if you're using push-pull MCU outputs. I would strongly recommend using push-pull for the clock if nothing else. If you're already doing this then I can't explain the issues you're seeing.1.3KViews0likes1CommentRe: Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock
@AqidAyman_Intel wrote: Okay, this sounds more like an RTL level issue rather than anything with the bitslip and LVDS IP. Maybe check the RTL viewer to see if synthesis is fanning out the bitslip_pulse signal to each bit of the bitslip control in the LVDS SERDES IP. I'm not using any SERDES IP. While I might agree an RTL investigation will prove the point, the issue is that this is dependent on synthesis, where there is no obvious way to lock down the relationship with cntsel[] and the clockout signals in the PLL IP.2.9KViews0likes0CommentsRe: Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock
Yes, you're entirely correct in that I have to perform multiple phase shifts (32) to invert a clock waveform. This is as expected and described in my post on the 25th September. However, you seem to be answering a completely different question to the one posed, ie the predictability of which PLL clock is shifted with cntsel set to a known value. My post of the 6th October illustrates the issue, where if I should increment the phase with multiple phase shifts with cntsel[4:0] set to a specific value and noting which of the output's phase changes in sympathy. For clarity I repeat below: cntsel[4:0] = 0, outclk0 phase undergoes a change cntsel[4:0] = 1, outclk4 phase undergoes a change cntsel[4:0] = 2, outclk2 phase undergoes a change cntsel[4:0] = 3, outclk5 phase undergoes a change cntsel[4:0] = 4, outclk4 phase undergoes a change cntsel[4:0] = 5, outclk3 phase undergoes a change cntsel[4:0] = 6, no clock changes phase cntsel[4:0] = 7, no clock changes phase This is the issue at hand and look forward to your reply.3KViews0likes0CommentsRe: USB Blaster driver for Max+plus II
For a simple solution with running Max-plus under Windows XP you might like to look at VirtualBox. This is a discussion on accessing a LPT device from within a virtual machine, it might assist in understanding the issues at hand. https://forums.virtualbox.org/viewtopic.php?t=54187 Otherwise, perhaps get an old PC with a real LPT / Centronix interface!4.3KViews1like3Comments