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Honored ContributorCyclone V PLL Dynamic Phase Shift
Hello,
did anybody successfully use basic PLL dynamic phase shift with Cyclone V? I tried to port an existing Cyclone III application, expecting that the dynamic phase shift interface would work as before, using scanclk, phase_en, updn, cntsel and phase_done PLL ports. According to documentation (AN661) it should. But phase_done is never asserted, either before or after setting the phase_en input. I wonder if there are additional requirements not mentioned in the documentation? Looking forward for any insights. Best regards, Frank3 Replies
Altera_ForumI found the problem. I had instantiated altera_pll directly in VHDL code as previously altpll for Cyclone III.
But without setting a pll_subtype parameter to "DPS" and some other accompanying parameters, the dynamic phase shift ports are left unconnected without a warning. Unfortunately there's no altera_pll user manual with port and parameter documentation, only AN661 giving usage examples. Altera is apparently assuming that the new PLL IP is only implemented through Megawizard.- Altera_Forum
I think you should open a ticket on altera mysupport.
- Altera_Forum--- Quote Start --- I think you should open a ticket on altera mysupport. --- Quote End --- Guess they'd tell me what I already know. DPS can be implemented through Megawizard, direct altera_pll component instantiation is unsupported respectively undocumented. The below VHDL instantiation works for me nevertheless. Regards, Frank
pll1_inst : altera_pll GENERIC MAP ( pll_type => "Cyclone V", pll_subtype => "DPS", operation_mode => "direct", m_cnt_hi_div => 15, m_cnt_lo_div => 15, n_cnt_hi_div => 256, n_cnt_lo_div => 256, c_cnt_hi_div0 => 1, c_cnt_lo_div0 => 1, c_cnt_hi_div1 => 1, c_cnt_lo_div1 => 1, c_cnt_hi_div2 => 2, c_cnt_lo_div2 => 2, c_cnt_hi_div3 => 2, c_cnt_lo_div3 => 2, c_cnt_hi_div4 => 2, c_cnt_lo_div4 => 2, c_cnt_hi_div5 => 2, c_cnt_lo_div5 => 2, n_cnt_bypass_en => "true", pll_vco_div => 2, pll_bwctrl => 6000, pll_cp_current => 20, pll_output_clk_frequency => "480.0 MHz", pll_fractional_cout => 32, reference_clock_frequency => "16.0 MHz", number_of_clocks => N_RX, output_clock_frequency0 => "240.0 MHz", phase_shift0 => "0 ps", duty_cycle0 => 50, output_clock_frequency1 => "240.0 MHz", phase_shift1 => "0 ps", duty_cycle1 => 50, output_clock_frequency2 => "120.0 MHz", phase_shift2 => "0 ps", duty_cycle2 => 50, output_clock_frequency3 => "120.0 MHz", phase_shift3 => "0 ps", duty_cycle3 => 50, output_clock_frequency4 => "120.0 MHz", phase_shift4 => "0 ps", duty_cycle4 => 50, output_clock_frequency5 => "120.0 MHz", phase_shift5 => "0 ps", duty_cycle5 => 50, output_clock_frequency6 => "120.0 MHz", phase_shift6 => "0 ps", duty_cycle6 => 50, output_clock_frequency7 => "120.0 MHz", phase_shift7 => "0 ps", duty_cycle7 => 50 ) PORT MAP ( rst => reset, refclk => clk16, scanclk => clk40, phase_en => phasestep, updn => phaseupdown, cntsel => std_logic_vector(phase_cnt_sel), outclk(N_RX-1 DOWNTO 0) => pll_out_clk, phase_done => phasedone, locked => pll_locked );
