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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V PCIe/DMA issues

I have a Cyclone V design with the the V-Series Avalon-MM DMA for PCI Express (yeah, I know it's been obsoleted, tell my S/W colleagues that). I did the first build with QPS 17.1; there have been ot...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

The Cyclone V PCIe AVMM DMA IP is not available in v19.1std, so you might not able to run the simulation in v19.1std


I'm using the example design (pcie_de_ep_dma_g2x4_cv.qsys) in the link below to generate the simulation testbench in v18.0std (v17.1std is not installed here), and it is passing the simulation.

\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\example_design\cv


Perhaps we can start the debug with this example design to determine if the same problem can also be observed before jump into the detail of your design.


Regards -SK