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Occasional ContributorCyclone V nCEO pin , what VCCIO when used as IO pin
Hello Simon,
The operating voltage for the configuration input pin is independent of the I/O banks power supply,
VCCIO, during configuration. You may refer on page 246 of Cyclone V Device Handbook from this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdfThe nCEO pin will comply with Table 15 from page 19 of that Cyclone V Device Datasheet when it is configured as general purpose I/O pin. Thus, the Vih value will depends on the I/O standard you set.
You are safe to put 3.3V of Vih to nCEO if you set 3.0-V LVTTL as I/O standard as situation you previously mentioned because the value of Vih can go up to 3.6V in that particular I/O standard.
Hope this clarifies.
Occasional ContributorHi
Thank you for getting back to me, but unfortunately you may have misunderstood my question.
For the 5CEFA9F23I7N device, the nCEO pin is within Bank 5A. I have VCCIO5A connected to 3V3, however VCCPGM is connected to 3V0.
I am planning on using the nCEO pin as a regular IO pin (input only).
In which case, is it safe to feed a 3V3 signal into the nCEO pin?
I ask as the documentation only mentions using a 10K pull-up to VCCPGM.
Best regards
Simon
Regular ContributorHello Simon,
I apologize for the confusion. To answer your question that will depends on configuration pins power supply (Vccpgm). You can refer on page 5 and page 9 from Cyclone V Device Datasheet to check for the range of Vccpgm. Here's the link to Cyclone V Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf
I hope this answer helps.
Thank you
- SHard2
Thank you for getting back to me.
The Cyclone V data sheet states that VCCPGM, for a '3.0V' supply, has a minimum of 2.85V to a maximum of 3.15V.
However, table 15 of the same document (page 19) states that the single ended IO standard for 3.0V LVTTL requires a 3.0V VCCIO, but allows a maximum input Voltage of Vih=3.6V.
So, just to clarify my question...
For the 5CEFA9F23I7N, the nCEO pin is within Bank 5A. I have VCCIO5 = 3V3 & VCCPGM = 3V0.
If nCEO is configured as a general purpose IO pin, does it comply with the single ended IO standard as described in table 15?
In which case, if the nCEO pin is configured as both general purpose IO 'and' 3.0V-LVTTL I can safely feed a 3.3V signal into the nCEO pin.
Is this correct?
Best regards
Simon
- AminT_Intel
Hello Simon,
I apologize for taking time to reply to your recent post.
If nCEO is configured as a general purpose IO pin, does it comply with the single ended IO standard as described in table 15?
Yes, it does comply with Single Ended I/O Standards in Table 15 from page 19.
In which case, if the nCEO pin is configured as both general purpose IO 'and' 3.0V-LVTTL I can safely feed a 3.3V signal into the nCEO pin.
That will depends on types of signal you are referring. If you are referring this signal as Vccio, then the maximum input voltage that you can put on 3.0-V LVVTL is 3.15V. If you are referring this signal as Vih, then you can put the value up to 3.6V.
In short, if you meant '3.3V signal' as Vccio then the answer is no it is not safe to feed that signal into nCEO pin. If you meant this signal as Vih, the answer is yet it is safe to feed it.
Do note that Vccio is a voltage to activate nCEO pin. Vih is for input high which means anything that is in the range of 1.7V to 3.6V will be read as logic 1 (HIGH) .
I hope this answer helps you. Please do not hesitate to ask more questions for clarifications.
- SHard2
Hi and thank you for getting back to me.
For final clarification, as I may have inadvertently confused things...
If the nCEO pin is configured as general purpose IO it will comply to its bank VCCIO which is 3V3.
I can therefore safely feed a signal with a Vih of 3V3 into the nCEO pin.
Best regards
Simon
