Altera_Forum
Honored Contributor
11 years agoCyclone V LVDS_RX IP
Hi all,
I am working with Cyclone V to implement lvds_rx. There is a different option about LVDS_Rx IP of cylone V devices compared with others series:"Is this interface constrained to the left, or right banks?". User guide says that This option determines the PLL compensation mode in Cyclone V devices. But It doesn't have detailed information about the difference between the PLL compensation in left or right banks and others banks, and i can't to evaluate the performance of this interface. I am looking forward your reply. Thanks.