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Altera_Forum
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11 years ago

Cyclone V LVDS_RX IP

Hi all, I am working with Cyclone V to implement lvds_rx. There is a different option about LVDS_Rx IP of cylone V devices compared with others series:"Is this interface constrained to the left...
Altera_Forum's avatar
Altera_Forum
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11 years ago

There is a fundamental difference in Cyclone V, as compared to previous families, to increase the performance of the LVDS interfaces. Whereas previously (e.g. in Cyclone IV) and LVDS I/O pin pair could be specified as input of output, Cyclone V has dedicated LVDS input and output pins.

So, there will be limitations as to where LVDS RX pairs can be placed. This may also affect which PLLs can be used for compensation.

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i can't to evaluate the performance of this interface

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How are you expecting to evaluate it? Are you hoping to take real measurements off a hardware platform?

Put your design together, constrain it and let Quartus tell whether it's good to go or not. Then relocate your LVDS rx pairs to the other side of the device (so, presumably, it uses a different PLL) and get Quartus to tell you whether it meets your constraints.

Regards,

Alex