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Spieler's avatar
Spieler
Icon for New Contributor rankNew Contributor
7 years ago

Cyclone V LVDS deserializer bitrate

Hi, I am writing to see if we can identify the reason why the LVDS receiver of our system has problems to receive the incoming stream properly. The incoming stream comes from an LVDS ADC (AD9257) ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi ,

Hope you the serdes circuit for the Cyclone V is using the dedicated circuitry in your setting.

As you said termination is an another point to note. Please ensure that the termination is on internally on the FPGA.

Regards,

Rs