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Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone V LVDS & DDR3 on same bank

Hello, I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements; - 32 bit DDR3 interface Top and Bottom (64 bit total) - 68 LVDS input p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you for letting me know. Like you I also thought of VCCPD to power LVDS input and VCCIO as irrelevant.

If you have a little example design that shows the Differential input termination on a 1.5V bank you could add it your service request and have them take a look at it. The fifth generation devices are pretty new so a bug in Quartus may also be possible.

Quartus 12.0 is coming out the next weeks so I would definitley wait for that when before rolling out your board. Although we don't use the LVDS input on a 1.5V bank, please keep on posting updates on this topic when you have new information or tried the clock input setup on your board.