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Altera_Forum
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14 years ago

Cyclone V LVDS & DDR3 on same bank

Hello, I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements; - 32 bit DDR3 interface Top and Bottom (64 bit total) - 68 LVDS input p...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Got the information today that it is not possible to use a 2.5V LVDS clock input on a 1.5V IO Bank of an ArriaV Chip. Just wanted to let you know...

The only strange thing is that Quartus will not bring up an error for this configuration, even when using differential termination on that pin pair.