Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Cyclone V LVDS & DDR3 on same bank

Hello, I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements; - 32 bit DDR3 interface Top and Bottom (64 bit total) - 68 LVDS input p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello,

Have not had any further info on this one, but it seems that we need the following:

VCCIO = 1.5V

VCCPD = 2.5V

While Quartus suggests that the OCT is OK under these conditions, I am waiting for release 12 to re-check it, and will also probably include off chip termination just in case. Although with 68 pairs, this is going to make the layout tricky...