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Altera_Forum
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14 years ago

Cyclone V LVDS & DDR3 on same bank

Hello, I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements; - 32 bit DDR3 interface Top and Bottom (64 bit total) - 68 LVDS input p...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hello FvM,

Thanks for the suggestion. I have made a simple project with LVDS inputs and set default I/O standard to 1.5V in the “Device and Pin Options” window. Also have 1.5V I/O in the same bank. So looks OK (even works if I use 1.2V).

However what is bothering me is that it also allows me set in the Assignment Editor for the LVDS inputs:

Input Termination = Differential

No errors

Does “Input Termination = Differential” mean that the LVDS receivers have on chip termination enabled?

Thanks, Ken