Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Cyclone V in Configuration Error Handling

Hi to everyone I built an evaluation board for myself with a lot of electronic and a cyclone V. The problem is, I can't communicate with the FPGA over JTAG. After analysing, I think the FP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Wondering if you ever fixed this. I'm seeing a similar problem except I can program through JTAG, but when I use Fast Passive Parallel, I see a similar behavior on the nSTATUS line.