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Altera_Forum
Honored Contributor
Honored ContributorCyclone V in Configuration Error Handling
Hi to everyone
I built an evaluation board for myself with a lot of electronic and a cyclone V. The problem is, I can't communicate with the FPGA over JTAG. After analysing, I think the FPGA is always in the Configuration Error Handling. The signal nSTATUS is released high and pulled low and so on. Could anybody give me some advice? I really don't know what to do. The nStatus is always toggling; it does not depend on everything. Even if i try to connect with my JTAG, the nSTATUS is always toggling...5 Replies
Altera_ForumI think you need to post some schematics to help us...
- Altera_Forum
So I uploaded my schematic from the whole JTAG part. One of you may see a mistake?
- Altera_Forum
So I did some pictures from the oszilloscope.
scope_2 and scope_3: 1=>TDI 2=>TMS 3=>TCK 4=TDO scope_4 nSTATUS - Altera_Forum
I have to suspect your power supplies. There's nothing particularly obvious that's wrong with the part of the schematic you've posted.
Does the toggling on nSTATUS look at all like the toggling you've captured on TDO? If TDO was behaving properly it should be responding at the same rate as the TCK or TDI signal you're driving in. Your scope trace shows 1ms per division. That is far too slow for any sensible behaviour. It's more likely to be directly linked to behaviour you have on an FPGA supply rail. Probe around your power supplies, look for any that are dropping out at any point or, more likely, repetitively. That might explain the behaviour you have on TDO and nSTATUS. I note that you've captured your 'EPCS' to accept either SO16 or SO8 parts. This clearly requires additional, unwanted tracking, but I can't see that coming into play here. Regards, Alex - Altera_Forum
Wondering if you ever fixed this. I'm seeing a similar problem except I can program through JTAG, but when I use Fast Passive Parallel, I see a similar behavior on the nSTATUS line.
