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Altera_Forum
Honored Contributor
10 years agoCyclone V HPS UART, can't rx data
I can send RS232 data via HPS UART1 but unable to read data. The scope shows RS232 data on RX pin but test code can’t read any data from /dev/ttyS1 and nothing when I ‘cat /dev/ttyS1’
I can think of multiple reasons but right now I’m double checking the FPGA implementation. The RS232 pins that are used for UART1 are different then default. This has been implemented opening QSYS and select the HPS system, then select ‘peripheral pins'. Scroll down to the UART Controllers. Set the UART1 to use the FPGA fabric for it’s pinout. After generating the HDL the uart pins show up for connection, these are brought up to top.vhd and connected to the correct signals. The correct pins and voltages levels are called out in top.qsf. Please see attached photos One question I regarding FPGA implementation: In QSYS should HPS pin mode be set to ‘FPGA’ or should be set to ‘HPS I/O set’ and then use LoanIO to map to different pins?12 Replies
- Altera_Forum
Honored Contributor
Thanks for the reply. Trying to communicate from external RS232 device to Cyclone through HPS Linux application software. Problem is the RS232 pins that are wired to Cyclone are different from the default UART1_TX, UART1_RX pins that come up when you click "HPS I/O Set 0".
I can draw up a block diagram of pins/connections if you'd like to dig in more. Also if routing to pins that aren't the default HPS I/O pins isn't a possibility can look into different solution. - Altera_Forum
Honored Contributor
--- Quote Start --- I can send RS232 data via HPS UART1 but unable to read data. The scope shows RS232 data on RX pin but test code can’t read any data from /dev/ttyS1 and nothing when I ‘cat /dev/ttyS1’ I can think of multiple reasons but right now I’m double checking the FPGA implementation. The RS232 pins that are used for UART1 are different then default. This has been implemented opening QSYS and select the HPS system, then select ‘peripheral pins'. Scroll down to the UART Controllers. Set the UART1 to use the FPGA fabric for it’s pinout. After generating the HDL the uart pins show up for connection, these are brought up to top.vhd and connected to the correct signals. The correct pins and voltages levels are called out in top.qsf. Please see attached photos One question I regarding FPGA implementation: In QSYS should HPS pin mode be set to ‘FPGA’ or should be set to ‘HPS I/O set’ and then use LoanIO to map to different pins? --- Quote End --- So for the HPS to use it, it should be set to "HPS I/O Set" something, for the FPGA then you set it to Loan I/O if using a controller in the FPGA, otherwise the UART itself will go to the FPGA. Really depends what you're trying to do here. Can you post clearer pictures? I'm not sure where you're trying to run pins to and from.