Honored ContributorI want to use all 6 transceivers for Gb Ethernet communication but I'm having trouble with the IP and assigning a TX PLL that is not from one of the channels as these are all used for RX.
Is it at all possible to use all 6 transceivers at once, and how do I then solve the TX PLL issue? I have connected a 125MHz LVDS clock to one of the Refclk inputs of the transceiver blocks.
Honored ContributorHi,
You would need to leave one unused RX channel for the CMU PLL purpose. Probably you could try to explore using fPLL to clock your channels.Honored ContributorOr you can look for larger device with additional transceiver channels ie 9 channels device.
Honored ContributorThat is also what I have arrived at at this point, but what sense is there in advertising that you have 6 transceivers (a transceiver is a combined TX/RX device) when you can always only use 5 of them at a time?
Is there really no other way to clock the transmitters than using of the channel CMU PLL's? The documentation is very hard to figure out and understand, and I'm having a hard time getting an clear overview of how things are connected and what's possible or not. The solution of using an even larger fpga would generate a huge price penalty which is not acceptable. We have chosen and designed around an fpga having 6 transceivers which is what we need, but I wouldn't in a million years have guessed that I could only to use 5 of them.Honored ContributorAs I read the literature, I should be able to source a fPLL from one of the RefClk inputs in the transceiver banks, and then use this fPLL to source all transmitters. All channel CMU PLLs are to be used as CDR PLLs.
***************************************************************************************** Transmitter PLL In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR) PLL. ***************************************************************************************** Is this possible?Honored ContributorIt is possible to use fPLL to clock all the 6 transmitters. You can try to test out a test design and run through Fitter compilation.
Honored ContributorThat's the answer we were looking for. Now we only need to make it work. No luck so far, but knowing that it at least can be done helps.
Honored ContributorWhat is the issue or Quartus error that you encounter?
Honored ContributorOur guy who is in charge of synthesizing the project, is right now working on a version with only 5 transceivers running so that software development has something to work with. But the main problem was that Quartus would not accept not using one of the transceiver channel CMU PLLs for the transmitters. I will have to get back to you when we get time to work on this issue again.
Honored Contributorlet me know when you have more details on the error.
Honored ContributorThank you, I'll do that but it may not be right away.
