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SimonRichter's avatar
SimonRichter
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone V GX, Native PHY, fPLL as TX PLL, per-channel divider and reconfiguration

Hi, after I've found a valid clock routing for using all transceiver channels in full-duplex mode with CDR on the receive path and the transmit path clocked by the fPLLs, two small questions remain...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.