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SimonRichter's avatar
SimonRichter
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone V GX, Native PHY, fPLL as TX PLL, per-channel divider and reconfiguration

Hi, after I've found a valid clock routing for using all transceiver channels in full-duplex mode with CDR on the receive path and the transmit path clocked by the fPLLs, two small questions remain...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


As I understand it, you have some inquiries related to the TX local clock division factor. For your information, this clock division is located inside the TX PMA. It allows you to use a single TX PLL frequency to achieve two different data rate which is a division by 2. For example, if you want to implement 3G and 1.5G. You can configure the fPLL to output 1.5GHz frequency (for 3Gbps). Then, when you would like to operate at 1.5Gbps, you can reconfigure the channel to have division of 2. With this, you do not need to reconfigure the fpll.


Please let me know if there is any concern. Thank you.