SimonRichter
Occasional Contributor
4 years agoCyclone V GX, Native PHY, fPLL as TX PLL, per-channel divider and reconfiguration
Hi,
after I've found a valid clock routing for using all transceiver channels in full-duplex mode with CDR on the receive path and the transmit path clocked by the fPLLs, two small questions remain:
- The "TX local clock division factor" setting, is that applied to the external PLL as well, or is that only available on the path from the CMU PLL to the TX PMA? If it can be used when using the fPLL as the TX clock source, can it be reached through the reconfiguration interface or is it fixed?
- Is there a similar mechanism for the RX PLL while it is locked to the reference clock?
The goal would be to select between 3Gbps and 1.5Gbps on a per-port basis.