New Contributor
ContributorHi,
I could not understand what you would like to implement with this part of your code.
process(CLK) --Sync PLL clock with 50 MHz oscillator
begin
if rising_edge(CLK) then
pll_clk_sync <= pll_clk;
end if;
end process;
From here, it looks like you are trying to sample pll_clk (500MHz) with a slower clock CLK (50MHz).
From an example below, if there's phase shift between two clocks, because the frequency of the pll_clk is 10 times that of the CLK, you can see that at every rising edge of CLK, the value of pll_clk is always the same, which means the pll_clk_sync won't change.
Another example below is when the phase difference between two clocks precisely aligns their rising/falling edges, at every rising edge of CLK, the pll_clk is also at an edge, so that the sampling value for pll_clk_sync could be an uncertain value. This is a big risk.
Best Regards,
Xiaoyan
New ContributorI was trying to synchronize the PLL clock with my 50 MHz oscillator clock, but at some point I understood that it was completely wrong and unnecessary. Anyway, first advise to change process sensitivity list solved my problem. Thank you for your help.
