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Vilius_Z's avatar
Vilius_Z
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone V GT 5CGTFD9D5F27C7N PLL can not lock to 50 MHz oscillator

Hi, I am an absolute beginner doing my baby steps in digital design with FPGAs, but I have some general electronics knowledge background. So excuse me for lack of common FPGA sense that someone mi...
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Programmable Logic Device
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

Your sensitivity lists are pointing to CLK instead of pll_clk. Should be

process (pll_clk)

and then use rising_edge(pll_clk)