Forum Discussion
Vilius_Z
New Contributor
New ContributorCyclone V GT 5CGTFD9D5F27C7N PLL can not lock to 50 MHz oscillator
Hi, I am an absolute beginner doing my baby steps in digital design with FPGAs, but I have some general electronics knowledge background. So excuse me for lack of common FPGA sense that someone mi...
sstrell
Super Contributor
Super ContributorYour sensitivity lists are pointing to CLK instead of pll_clk. Should be
process (pll_clk)
and then use rising_edge(pll_clk)
