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Honored Contributor
Honored ContributorCyclone V Fractional PLLs don't output expected clock frequency
I'm using Quartus 17.0.2. I have trying to generate a 148.5MHz clock with a 50MHz input reference clock. When I put the PLL in fractional mode and enter 148.5M as my target frequency the megawizard s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yep, I actually tried that already. The design will actually elaborate, however just before synthesis finishes is spits out about 100 different syntax errors related to other altera library modules. This is a mess!! --- Quote End --- Sounds like you need to file a support request with Altera to inform them their software has a problem ....
