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Altera_Forum
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8 years ago

Cyclone V Fractional PLLs don't output expected clock frequency

I'm using Quartus 17.0.2. I have trying to generate a 148.5MHz clock with a 50MHz input reference clock. When I put the PLL in fractional mode and enter 148.5M as my target frequency the megawizard s...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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in the short term one could probably just comment out the reference .refiqclk_1(), on line 2163 of file altera_pll.v as a quick fix, as the ports are not connected and in this context do nothing useful.

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Yep, I actually tried that already. The design will actually elaborate, however just before synthesis finishes is spits out about 100 different syntax errors related to other altera library modules. This is a mess!!