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Honored Contributor
Honored ContributorCyclone V E Development Board Kit
Hi all, I have Cyclone V E Development board kit. In the user guide, it said the frequency could go up to 810 MHZ by using Clock Control Application. But in the Cyclone V datasheet, it said "Glo...
Altera_ForumHonored Contributor
Honored ContributorThe Global Clock Networks are used to route the Clock signals to various parts in the FPGA. These are specialized clock tree networks that have low Jitter and delay. This means that they can route clocks with a max frequency of 460MHz. This will be the same as that of the Max output frequency fmax-out of the PLL. Clock Tree networks are optimized for those particular frequency ranges. Running clocks more than this rated freq may produce unwanted glitches or jitters.
