Cyclone V E Development Board Kit

The Global Clock Networks are used to route the Clock signals to various parts in the FPGA. These are specialized clock tree networks that have low Jitter and delay. This means that they can route clocks with a max frequency of 460MHz. This will be the same as that of the Max output frequency fmax-out of the PLL. Clock Tree networks are optimized for those particular frequency ranges. Running clocks more than this rated freq may produce unwanted glitches or jitters.