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Let me clarify this:
1. The Cyclone V E dev Kit has an external on-board programmable oscillator Si570 whose frequency range is 10Mhz to 810MHz. This means that you can use this Si570 oscillator to generate any frequency between this range. You could use this as an input to the FPGA also.
2. The Cyclone V Series FPGA thats on the board has 4 PLLs, whose max frequency is 560-660MHz. This means that these PLLs, depending on the exact device, can generate clocks with a maximum frequency of 550-650MHz. The core logic in the FPGA may be optimized for these operating frequency ranges to ensure you do not have any clock jitter/routing issues as well as timing issues.
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Thank you so much for your info. How about's clock network? Global Clock Network and Regional Clock Network? What are they used for? In the Cyclone V Data sheet, it shows that their max is 460Mhz. It makes me confusing with programmable si570 oscillator.
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