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Honored Contributor

10 years ago

Cyclone V E and DDR3 connection

Hi I did a FPGA Board on myself and I don't get the DDR3 working correctly. While reading the "External Memory Interface Handbook Volume 3: Reference Material" and the calibration I got th...

Altera_Forum

Honored Contributor

10 years ago

I think solution id: rd06102013_643 (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06102013_643.html) covers this. Bit swapping within a byte lane is fine. However, if you want to move DQS pins you need to move all the DQ pins within that group with it.

Cheers,

Alex

Forum Discussion

Cyclone V E and DDR3 connection

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