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comccmoc's avatar
comccmoc
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3 years ago

Cyclone V dedicated flash pins with generic serial flash interface

I am getting "Illegal constraint of I/O pad" errors when attempting to connect a GSFI IP to top level I/O corresponding to the NCSO, DCLK, and DATA[3..0] pins, even though I have it set in the GSFI I...
comccmoc's avatar
comccmoc
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3 years ago

Sorry for the late reply, I have been unable to login for some time.

https://www.intel.com/content/www/us/en/docs/programmable/683419/22-2-20-2-1/flash-access-using-the.html

"Disable dedicated AS interface" and "Enable SPI Interface" only enabled when want to access the general purpose QSPI flash (user I/O) or for Intel® MAX® 10 devices.


I am taking that to mean these settings can be left unchecked because I am on a Cyclone V?

So I have my Generic Serial Flash Interface with outputs to internal signals that just terminate in the file that instantiates them? I believe I have tried that but the fitter does not route them to the dedicated I/O pads.

Maybe I am forced to use Platform Designer with the Nios processor to make this work?

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Ya those settings can be left unchecked if you're using EPCQ flash since not need to explicitly connect to the FPGA external PIN.

May be you can try to use Platform Designer with the Nios processor and refer to the document steps.