Honored Contributor
Honored ContributorI find it hilarious that that the documentation for these dev kits still doesn't specify the pin mapping to physical pin numbers on the header.
The DE1-SoC manual has a nice table which says "pin assignment of the two GPIO headers" which gives you FPGA pin numbers and maps them onto the completely arbitrary names that are used in the top level file. The add-on boards like the LT24 have a nice table which it calls "pin assignments for the 2x20 GPIO pins in Quartus II", that maps the function of the board to physical pin numbers on the 2x40 header, which in itself tells you nothing about the "pins in Quartus II". To actually find out what connects where you have no choice but to resort to reading it off the schematic - which in itself is a pain given that the provided schematic has a nice watermark across it that is so opaque you can barely read anything, yes Terasic, I know you designed the schematic, I don't need you shoving it in my face while I'm trying to work out what you've done. So what is the point in the two tables when they don't actually tell you an actual physical relationship. Altera and Terasic seriously need to get themselves in order given how much of a joke the documentation and IP is. --- In fact for anyone who finds this through Google and doesn't want to go through the schematic, I've annotated the GPIO pages from the user manual of the DE1-SoC (attached to post) with mapping - I'll do Altera's job for them so you don't have to.
