Cyclone V: Connecting the HPS EMAC via FPGA fabric IO

I am having issues meeting timing when bringing an HPS EMAC into the fabric using a Cyclone V device. My project is connected as shown below where I am using the hps_interface_splitter and gmii_to_rgmii_adaptor cores.

I have added an 8nS clock constraint to both RGMII_RX_CLK and RGMII_TX_CLK, but when I build the design I am getting large timing violations on the GMII_RX_DATA[7..0] between the HPS EMAC and the fabric register it feeds.

Violations:

First failing path shown in “Technology Map viewer” where this is between a fabric register located in the GMII_to_RGMII core and the HPS EMAC:

Same path shown in “Chip planner”:

The big delay that seems to be causing the issue is this 7.614nS, that if I understand correctly is the delay within the HPS? (i.e. nothing to do with fabric timing)

Can someone give me any pointers on how I can get this to meet timing please? I am assuming I am doing something inherently wrong here such as have the EMAC incorrectly wired up with the 2 fabric cores.

Thanks for any help!