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Altera_Forum
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10 years ago

Cyclone V clock output pins

On the Cyclone V C3 device there are pins called FPLL_BL_CLKOUT0 and FPLL_BL_CLKOUT1 and similar pins on the other side FPLL_BR_CLKOUT0 and FPLL_BR_CLKOUT1. The implication is that they are specialis...
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Altera_Forum
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9 years ago

I have a similar question to this. I'm designing a DDR3 interface in a Cyclone V 5CEBA5 F484 device. I'm using bank 4A as the interface because it has 48 pins of which I'm using 40. There are no PLL clock out pins in this bank so I've allocated 2 CLKIN pins, CLK2p and CLK2n for my DDR_CLK and DDR_CLK_N outputs. The fitter hasn't 'complained' so my question is are these clock outputs being treated as ordinary I/O whose delay will change each time it's run through Quartus?

Thanks,

Clive