cyclone V caacading fpll for sdi ii(transceiver) xcvr_refclk filter error?

Hi,

Regarding the cascade PLL, it seems like you are using one fPLL driving another fPLL which then drive the SDI II IP's refclk. For your information, in the transceiver generally one fPLL driving the refclk which then drive the TX PLL is only. My experience is two fPLL might trigger error.

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Hi,

Regarding the cascade PLL, it seems like you are using one fPLL driving another fPLL which then drive the SDI II IP's refclk. For your information, in the transceiver generally one fPLL driving the refclk which then drive the TX PLL is only. My experience is two fPLL might trigger error.

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Thank you for your reply.

I try one fpll to drive the refclk,but it filter error.https://www.alteraforum.com/forum/attachment.php?attachmentid=10865

I don't know why.

Do you how to set pll location and global clock?

Hi,

You might want to use RTL viewer to look into the SDI II IP to see if there is any fPLL already instantiated. I am not familiar with SDI II IP but just to double check in case the IP itself have had fPLL inside. Then it might conflict with your external fPLL.

To set PLL location, this is what I generally did:

Use RTL viewer, look for the target PLL instance ie fPLL, right click on the instance, locate in assignment editor. Then go to the Assignment Editor, and set the location for the PLL location.

hi, i'm running into similar fitter error with my cyclone v design with transceiver using quartus 15.0.150, with quartus 14.1 my design does not have these errors

do you use quartus 15? maybe 14.1 worth a try and plz give a feedback because i'm also struggling with this error and can not get my design working with quartus 15 but 14.1 it works fine

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hi, i'm running into similar fitter error with my cyclone v design with transceiver using quartus 15.0.150, with quartus 14.1 my design does not have these errors

do you use quartus 15? maybe 14.1 worth a try and plz give a feedback because i'm also struggling with this error and can not get my design working with quartus 15 but 14.1 it works fine

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I use quartus14.0.

I have not yet solve it. I use fpll to support the sdi refference clk.

do you know fPLL Cascade Clock Network?http://www.alteraforum.com/forum/attachment.php?attachmentid=10870&stc=1

Hi,

As described in the device handbook, on each side of the device, there are only two fPLL cascade clock lines. There are chances that your design somehow require more than two cascade clock lines which lead Fitter error.