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Altera_Forum
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10 years ago

Cyclone V ALTLVDS_TX: MSB inversion and timing constraints

Hello everyone, I'm designing a board with a Cyclone V driving a DAC running at 420MS/s using a parallel DDR interface. To achieve this datarate (840Mb/s per stream), there is an ALTLVDS_TX com...
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Altera_Forum
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10 years ago

your figures of sample rate, stream rate are not clear to me but anyway if you are sure of multicycle of 4 then setup mcp would be 4 and hold mcp would be 3.

Your timing case is that of DDR io output constraints. You need to check your DAC requirements and translate that to set_output_delay for Timequest. see examples in timequest resource centre at altera.com

Regarding msb inversion. Who asked to do that??? if just DAC behaves ok by experimenting on this bit then the possibility is your DAC supports offset binary. Conversion between 2's complement and offset binary is by inverting msb.