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Altera_Forum
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8 years ago

Cyclone V A9 DDR3 calibration fail no reboot ,but JTAG is OK

Dear All, help me analysis. I have a custom board with cyclonev and DDR3 (mt41j256m16tw-107it. In quartus ii v15.1.0 (64bit) I created Uniphy external DDR3;when I download sof file to FPGA th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

How soon after power-up/configuration is the calibration done? Are the supplies stable at that point?

Hold the Phy in reset for longer after power-up before allowing calibration to proceed.

Cheers,

Alex