Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

We are not aware of any examples showing how to make the location assignments for the PLL counters. I have made PLL location assignments before, but that used post-compile node names to lock down PLLs to specific locations. In this case, you need pre-synthesis or design entry names to make the assignments. I suggest trying to re-create this in some fashion in Quartus – create a simple design with a PLL and duplicate the frequency and phase on multiple output counters. Then see if they get synthesized into one clock.

If they do, then try making the location assignments to the PLL output counters. I used Design Entry all names as my filter in the node finder. Make it a location assignment, and for Value you need to specify PLL Output Counter as the element by double clicking the 3 dots. Then you have to figure out the x, y, and z locations. I don’t think we document locations to that detail, I think we only show locations for the PLLs. You can probably find x,y,z coordinates in the chip planner or start with a successful compile and check the PLL Usage Summary report to see one valid PLL counter location, then use that as a reference to make the assignments.

The hardest part is getting the right nodes, you need to be sure the output clocks are children of a PLL instance in the node finder.