Occasional Contributor
Regular ContributorThe only way I can think that the same clock would get affected by more than one selection of cntsel[] would be if some of the cntsel bits are tied to a static value by mistake. The only exception is when all of the cntsel bits are high, then all of the clocks will be phase shifted at the same time. Maybe you can put the cntsel bits in signal tap and verify they are toggling as expected?
Occasional ContributorI can confirm I have used signal tap to verify the cntsel[4:0] bits within the PLL module, the horses mouth so to speak, and they are set as expected.
The cntsel[4:0] are not static, but it seems that synthesis will move the bits to suit.
Driving gignals are confirmed as per "Figure 5: Waveform Example for Dynamic Phase Shift with Altera PLL IP Core" in "Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores". A waveform is attached to an earlier post.
What is especially curious is that more than one cntsel[4:0] value will affect the same clock. There is a throw away mention in the above document:
"When the PLL has two clocks with 0 degree initial phase shift between the clocks, the Fitter synthesizes
away the second clock automatically. To prevent the clocks from merging, Altera recommends
manually performing location constraint for each of the PLL output counters which share the same
frequency and phase shift".
How would I do this? Are there any examples?
Super Contributor
