Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

Hello,

I have found out that way back you had to address the physical counter locations, this was prior to version 13.1 as stated on page 14 of AN 661. Users had to look at the PLL usage report to see where there counters were physically placed and then address those locations on the CNTSEL ports to phase shift those counters. It was really confusing.

Then starting in 13.1, users were able to target the counters as they set them in the RTL, so that’s the “logical counter” ordering. If the clock output is on C0 in the IP, then the customer sets CNTSEL to 00000 to phase shift that clock.

I have a chance to connect with other FAE and they recently talked to a Cyclone V customer using dynamic phase shifting on multiple clock outputs and it was working fine. Next steps for you is to verify the version of Quartus and if it’s prior to 13.1 (not likely), then that could explain the problem. If it’s a current version, then the next step would be to confirm the CNTSEL ports are connected as expected.

Regards,

Aqid