Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

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@AqidAyman_Intel wrote:

Okay, this sounds more like an RTL level issue rather than anything with the bitslip and LVDS IP. Maybe check the RTL viewer to see if synthesis is fanning out the bitslip_pulse signal to each bit of the bitslip control in the LVDS SERDES IP.

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I'm not using any SERDES IP.

While I might agree an RTL investigation will prove the point, the issue is that this is dependent on synthesis, where there is no obvious way to lock down the relationship with cntsel[] and the clockout signals in the PLL IP.