Cyclone V: A PLL with multiple clocks and independently adjusting phase of a clock

Hello,

Apologies for the delay and inconvenience caused. I can now focus for your issue.

Based on the parameters you provided, the VCO effective frequency is 450MHz, so there are 8 VCO periods for each 56.25MHz output clock. That means there are 64 phase shifts available for each of those 56.25MHz output clocks to roll through one output clock period. I say “effective” VCO frequency because in reality the VCO is running at 900MHz. 450MHz is lower than the supported VCO operating range, there is a post scale VCO counter that is often used to support lower frequencies, so it divides the VCO frequency in half. The compilation fitter report – PLL usage/summary will show the value of this post scale counter. For phase shift calculations, you use the VCO frequency reported by Quartus, which is after the VCO post scale counter, so 450MHz in this case.

You may be able to see a change after several phase shifts, but for accurate phase measurements you should route the clocks to I/O pins that can be scoped on the board. The phase shift resolution is 270ps, and you are sampling signal tap at a 4.4ns period, so you would need over 16 phase shifts to see a change in signal tap.

When implementing dynamic phase stepping, you can specify either an individual output clock, or all of the output clocks depending on what you drive to the cnt_select port of the PLL IP. Table 4 of AN 661 shows how to set the cnt_sel port. A value of 11111 shifts all of the output clocks simultaneously.