Occasional Contributor
Occasional ContributorI increased the number of outputs to 8 to check which clock output had a phase-shift for which value of cntsel[4:0]
Where:
cntsel[4:0] = 0, outclk0 phase undergoes a change
cntsel[4:0] = 1, outclk4 phase undergoes a change
cntsel[4:0] = 2, outclk2 phase undergoes a change
cntsel[4:0] = 3, outclk5 phase undergoes a change
cntsel[4:0] = 4, outclk4 phase undergoes a change
cntsel[4:0] = 5, outclk3 phase undergoes a change
cntsel[4:0] = 6, no clock changes phase
cntsel[4:0] = 7, no clock changes phase
I note a throw away comment in AN-661 (Implementing Fractional PLL Reconfiguration with
Altera PLL and Altera PLL Reconfig IP Cores)
"When the PLL has two clocks with 0 degree initial phase shift between the clocks, the Fitter synthesizes
away the second clock automatically. To prevent the clocks from merging, Altera recommends
manually performing location constraint for each of the PLL output counters which share the same
frequency and phase shift."
After looking at the report file I can confirm each of the output counters (PLLOUTPUTCOUNTER_X54_Yy_Nn) are different for all outputs. Implying the clocks are not merged.
Any help would be most welcome.
Occasional ContributorIf I move the clock I use on the PLL IP module outclock ports the following change:
cntsel[4:0] = 3, now no change in any output clock phase
cntsel[4:0] = 7, outclk5 phase undergoes a change
It seems the optimiser/synthesiser regarding the PLL IP module moves ports around inconsistent without moving cntsel[] in sympathy.
Is there a way of stopping this and keeping the outclock ordering without the compiler moving ports around?
