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jbo's avatar
jbo
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone V (5CEF5A) with 2 QSPI Flashes

Hello,
I want to connect 2 QSPI Flashes on a Cyclone V device (5CEFA5).
One on the dedicated configuration pins and one on I/O pins to get an extra data storage.
Even HDL design was created in Platform Designer without any error the Quartus ‘Analysis&Sythesis’ always stops with a variety of error messages depending on the IP’s I’m using.
Any hint how to solve that?

Please note, project generation works fine if I'm using one QSPI Flash either for configuration or exported to I/O pins.

Configuration

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Without seeing the design or the error messages you are seeing, it's hard to say what's going on. More detail needed.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Jbo,


    As mentioned by Sstrell, it's difficult to analyze the issue without specific error messages or codes. Could you let us know the configuration scheme you're using? In the meantime, you may want to refer to the configuration user guide for additional guidance - Cyclone® V Device Handbook.


    Regards,

    Fakhrul


  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    As we do not receive any response from you to the previous notification that we provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    • jbo's avatar
      jbo
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hello sstrell, hello Fakhrul,

      sorry for the late response. I was sick the last few weeks not able to get access from home.

      I've attached the NiosSystem file in a first step. This was working to compile the 'Top Design'.
      Unfortunately, the 'Top Design' has links with reference to many modules. Therefore, it's not possible to make one zip file to attach it, too.
      I'll work on that.
      Please remember, the Platform Designer was able to add a seconed QSPI Flash but compilation reports some errors.

      Just for your information - my job was to replace the FPP configuration to ASx4 and to add a second QSPI Flash to further data storage.
      Please refer to the attached configuration 'Config.png'.

      As next step I will add a second QSPI Flash to generate the error message again.
      I'll come back as soon as possible.
      If you have any idea how to add it, please let me know.

      Thanks for your help

      Josef

      • jbo's avatar
        jbo
        Icon for New Contributor rankNew Contributor
        1 year ago

        Hello,
        I've just added a QSPI Flash configured to disable the dedicated Active Serial interface and to enable the SPI pins interface.
        The complete Nios System is in CAN.7z.

        Generate HDL is working fine but synthesis of the 'Top Design CAN' has reported error in the QSPI macrofunction.
        Refer to screen shot QSPI-Error.png.
        Anything seems to be wrong that generatd HDL design and the macrofunction doesn't match.

        VHDL file of my 'Top Design CAN' is attached too.

        Do you have any idea what's the reason for this mismatch?

        Thanks

        Josef