Honored Contributor
Honored ContributorAccording to Cyclone V datasheet, -7 speedgrade doesn't handle 875 MBPS. It's the maximum achievable bitrate with -6 speedgrade.
Operating the serial receiver near the speed limit suggests to use a PLL dynamic phase shift feature and implemenent an automatical clock phase adjustment. I haven't yet implement serial ADC interfaces with Cyclone V, thus I can't help you with the device related details. With Cyclone III and IV, that only have software SERDES, I found it more convenient to build my own SERDES block based on DDIO and PLL function, because the ALTLVDS_RX implementation has several restrictions.
