CYCLONE V - HPS and I2C Peripheral Pin

don't worry

In the meantime, I've done some other tests and I've to admit that it is a mess:

In particular, I've tried to drive both peripheral i2c0 and i2c1 to FPGA in the same exact way and their behavior is totally different:

- i2c1 presents the malfunctioning I mentioned in the previous posts (wrong frequency and duty cycle) when drived to FPGA but it works properly when driven to the devoted pins.

- i2c0 presents a correct frequency and the data shape is OK but it completely ignores the ACK received from the device, (even if present)
ad it limits the entire communication to send the first byte (i.e. the address of the device) then it releases the bus and does not send anything else.

I2c2 and i2c3 is not available via software without a suitable preload.

Is it possible that the problem is in the preload?