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Altera_Forum
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11 years ago

Cyclone V - Counter not counting correctly

Hi, I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here. My (serious) problem is...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks back for your thanks! :)

...And need be always add in your out-of-FPGA signals as MISO and N_DREADY in simulator any random delay ! :)

And may we ask Altera to add warning on compilation in similar "bare-in" situations without triggers ? :)