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Altera_Forum
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11 years ago

Cyclone V - Counter not counting correctly

Hi, I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here. My (serious) problem is...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You don't need to be that safe, this kind of solution is mostly used for debouncing switches. In your case I think that using 2-3 registers in series and directly take the output of the last register as input to your state machine should be enough. Try and search "metastability" and "FPGA" on the net and I think you'll find lots of information about that subject.