Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Cyclone V - Counter not counting correctly

Hi, I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here. My (serious) problem is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Daixiwen,

you pointed it out!

Since I send the n_dready signal through 3(!) registers and wait for all to have '0' in them, it just works!!!!!

Thanks to you and also to WitFed for your time and hints!!!! Gives me something to think about in my current and future designs!

Maik