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Altera_Forum
Honored Contributor
Honored ContributorCyclone V - Counter not counting correctly
Hi, I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here. My (serious) problem is...
Altera_ForumHonored Contributor
Honored ContributorThis could be a stupid question but are you using the right clock in Signaltap? Is it the same than in your process?
Are all your input signals on that state machine correctly synchronized with the clock? If they come from a different clock domain or from outside the FPGA they could require proper synchronization using at least two registers in series to avoid metastability issues.
