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Altera_Forum
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12 years ago

Cyclone PLL output clock pin assignment

Hi, I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively. My first question, how many off-chip output clocks are there for each dedicated PLL? ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks Pete for your reply.

Still need your clarification to my question. Based on your reply can i suppose each PLL doesn't have more than one clock output?

That means if i use PLL3_CLOCKOUTp pin as a single ended output clock i could not use PLL3_CLOCKOUTn as a second clock output from the same PLL3. Right?

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